Field of the Invention
The present invention relates to a wiring pattern manufacturing method and a transistor manufacturing method.
Background
In the related art, chemical plating (electroless plating) which is a plating method that utilizes reduction of a material surface according to a contact action is known. Since electric energy is not used in electroless plating, it is possible to apply plating to a resin material, a glass, and the like as a nonconductor.
However, a poor plating material such as a resin material or a glass has weak adhesion to the formed plating film, and the plating easily causes abrasion such as peeling and swelling due to internal stress in the plating film.
Therefore, a method is used in which an etching process is applied to the surface of a substrate by using a chromic acid solution or the like and the surface is chemically roughened. Thereby, the plating film to be formed is formed so as to penetrate into the corrugation of the roughened resin material, and therefore, it is possible to obtain an adhesion force (anchor effect).
In addition, a method is disclosed (refer to Japanese Unexamined Patent Application, First Publication No. 2006-2201) in which a base film of SOG (Spin-on Glass) or porous SOG is provided on a surface of a poor plating substrate to apply electroless plating on the base film, or a method is disclosed (refer to Japanese Unexamined Patent Application, First Publication No. 2008-208389) in which a base film that consists of a filler component such as a fine powder silica and a resin composition component is provided on a substrate surface to apply electroless plating on the base film.